Due to the progress of semiconductor fabrication technology and the improvement of electrical performance on semiconductor devices, along with increasing demands for various kinds of portable products in the fields of communications, networks and computers, semiconductor packaging technology such as Ball Grid Array (BGA), Flip Chip and Chip Size Package (CSP), which can reduce the size of a semiconductor package having higher pin counts, has become the mainstream.
For the flip-chip semiconductor package, a plurality of solder bumps are implanted on a plurality of bonding pads formed on a semiconductor substrate such as a wafer or a chip, and the solder bumps are electrically connected to a carrier such as a substrate directly. Compared to a wire-bonding method, the flip-chip semiconductor package has a shorter circuit path and is better in electrical performance, and further the flip-chip semiconductor package has enhanced heat dissipating performance when a back side of the chip thereof is exposed to the ambient.
As disclosed in U.S. Pat. Nos. 6,111,321, 6,229,220, 6,107,180, and 6,586,323, an Under Bump Metallurgy (UBM) is formed before forming a solder bump on a semiconductor substrate such as a chip when using the flip-chip technology, so as to bond the solder bump to the chip via the UBM. However, when the solder bump on the chip is electrically connected to a substrate directly, stress resulted from CTE (coefficient of thermal expansion) mismatch between the chip and the substrate would be imposed on the solder bump and the UBM, thereby causing cracking of the solder bump or delamination of the solder bump from the UBM. As a result, the electrical performance and reliability of the semiconductor package are adversely affected. To eliminate the aforementioned problems, as described in U.S. Pat. Nos. 5,720,100, 6,074,895, and 6,372,544, an underfill material is utilized to fill a gap between the chip and the substrate so as to alleviate the stress exerted to the solder bump and the UBM. However, the underfilling process alone is not satisfactory in eliminating the aforementioned problems and is time-consuming to carry out.
Another approach for solving the cracking and delamination issues is referred to as Re-Passivation, which is a method for forming on a passivation layer of the semiconductor substrate a dielectric layer made of such as benzo-cyclo-butene (BCB) or polyimide (PI), prior to the formation of the UBM. By the dielectric layer, the stress exerted to the solder bump and the UBM can be reduced. The re-passivation method is illustrated with reference to FIGS. 1A to 1E.
As shown in FIG. 1A, firstly, a semiconductor substrate 10 having a plurality of bonding pads 11 (I/O connections) is covered by a passivation layer 12 having a plurality of openings for partly exposing each of the bonding pads 11. For the purpose of simplifying illustration, merely a bonding pad 11 on the semiconductor substrate 10 is depicted in each of the accompanying drawings. Then, as shown in FIG. 1B, a dielectric layer 13 made of such as polyimide is formed over the passivation layer 12 and exposes the bonding pad 11. As shown in FIG. 1C, a UBM 14 is formed on the bonding pad 11 by a sputtering or plating technique. Then, as shown in FIG. 1D, a solder mask 15 such as a dry film is coated on the dielectric layer 13, leaving the UBM 14 exposed in order to coat a solder material 16 on the exposed UBM 14. Finally, after in turn performing a first reflow process on the solder material 16, removing the solder mask 15, and performing a second reflow process on the solder material 16, a solder bump 17 as shown in FIG. 1E is thus obtained.
The foregoing problems of cracking and delamination can be reduced by the above arrangement when a line width between circuits formed in the semiconductor substrate is not smaller than 0.13 μm. This is because the dielectric layer 13 formed between the UBM 14 and the passivation layer 12 is capable of absorbing the stress exerted to the UBM 14 and the solder bump 17. However, when the line width is smaller than 90 nm or even reduced to 65 nm, 45 nm or 32 nm, to overcome the resistance/capacity (RC) time delay induced by the reduction of line width, a dielectric material with low dielectric constant (low K) should be introduced to form the dielectric layer 13. By the use of the dielectric material with low dielectric constant, metal circuits formed in the semiconductor substrate can be closely arranged, such that signal leakage and interference can be prevented and the transmission speed can also be relatively enhanced. However, the dielectric material with the low K feature is hard and crisp in nature such that delamination of the dielectric layer may easily occur and the electrical performance is adversely affected. It is mainly because the stress is still primarily exerted to an interface between the solder bump 17 and the UBM 14, whereas the dielectric layer 13 formed under the UBM 14 can only relieve a portion of the stress in a lateral direction. As the dielectric layer 13 fails to provide sufficient buffer to alleviate the stress, cracking of the solder bump 17 or delamination of the UBM 14 may still occur.
Accordingly, as described in U.S. Pat. Nos. 6,492,198, 6,287,893, and 6,455,408, a Re-Distribution technology is developed to solve the above-mentioned problems, which involves the use of a re-distribution layer (RDL) for forming conductive circuits. By way of the re-distribution technology, bonding pads on a semiconductor substrate can be re-distributed to predetermined positions that allow better formation of UBMs thereon. Typically, a dielectric layer is formed under solder bumps in the re-distribution process, so as to allow the dielectric layer to provide certain buffer against the stress and thereby prevent cracking of the solder bumps or delamination of the UBMs. However, the performance of re-distribution process increases complexity, difficulty and costs of the overall fabrication processes, and problems such as parasitic capacitance arise due to the re-distribution of conductive circuits, which accordingly adversely affect the electrical performance of the semiconductor substrate.